1. Field of the Invention
The present invention relates to a mux scan cell, and more specifically, to a mux scan cell that contains a delay circuit for reducing occurrence of hold-time violations during testing procedures.
2. Description of the Prior Art
After integrated circuit chips are manufactured, tests are performed on the chips to verify whether the chips are good or bad, and the bad chips are thrown away.
Please refer to FIG. 1. FIG. 1 is a block diagram of a mux scan cell 10 according to the prior art. The mux scan cell 10 comprises a multiplexer 12 connected to a flip-flop 14. The multiplexer 12 has a first input 16 for receiving normal data D, a second input 18 for receiving test data TD, a selection input 20 for receiving a selection signal SEL, and an output 22 for outputting either normal data D or test data TD to an input 24 of the flip-flop 14. The flip-flop 14 has a clock input 26 for receiving a clock CLK and an output 28 for outputting a value that is present at the input 24 of the flip-flop 14 during an active edge of the clock CLK.
Please refer to FIG. 2. FIG. 2 is a block diagram of a mux scan chain 30 according to the prior art. The mux scan chain 30 comprises a first mux scan cell 11 and a second mux scan cell 13 that are identical to the mux scan cell 10 of FIG. 1 . The first and second mux scan cells 11 and 13 are serially connected together to form the mux scan chain 30. The multiplexers 12 in each of the first and second mux scan cells 11 and 13 are connected to the selection signal SEL in order to switch between testing mode and normal mode.
In testing mode, data Q0 is input directly to the first mux scan cell 11 for inputting test data TD. This data Q0 travels through both the multiplexer 12 and the flip-flop 14, and is outputted from the first mux scan cell 11 as data Q1. Likewise, data Q1 is input directly to the second mux scan cell 13 for inputting test data TD. This data Q1 travels through both the multiplexer 12 and the flip-flop 14, and is outputted from the second mux scan cell 13 as data Q2.
In normal mode, a slightly different approach is used. Since normal mode is the actual operation mode of the mux scan chain 30, combinational logic 32 is used to transform data Q0 and Q1 into normal data D of the first and second mux scan cells 11 and 13, respectively. That is, data Q0 first travels through combinational logic 32, next enters the first mux scan cell 11, and then is outputted from the first mux scan cell 11 as data Q1. Likewise, data Q1 first travels through combinational logic 32, next enters the second mux scan cell 13, and then is outputted from the second mux scan cell 13 as data Q2. In order for the mux scan chain 30 to function properly, data Q0 and Q1 must satisfy setup and hold times of the flip-flops.
Unfortunately, clock skew can cause problems for the mux scan chain 30. The presence of clock skew in the mux scan chain 30 can affect test mode operation differently than normal mode operation because the path delay associated with test mode is shorter than the path delay associated with normal mode. Please refer to FIGS. 4A and 4B. FIGS. 4A and 4B are timing diagrams of the mux scan chain 30 without clock skew and with clock skew, respectively. Symbols Qn−1 and Qn are used to symbolize pairs of signals such as the signals Q0 and Q1 or the signals Q1 and Q2. For this discussion, a rising edge of the clock CLK will be treated as an active edge of the clock.
As shown in the timing diagram of FIG. 4A, at time t0, Qn−1 has a binary “1” value when the clock CLK rises. Thus, since Qn previously had a binary “1” value, and Qn−1 had a binary “1” value when the clock CLK rose, Qn continues to have a binary “1” value after time t0. Notice that the value of Qn−1 changes at time t1, which is after the active edge of the clock CLK at time t0. When the next active edge of the clock CLK occurs at time t4, Qn−1 has a binary “0” value. Thus, the value of Qn changes to binary “0” shortly after time t4. Therefore, during test mode operation of the mux scan chain 30, both setup and hold times of the Qn−1 signal are satisfied with respect to the active edge of the clock CLK.
In FIG. 4B, the clock CLK is skewed by the amount of time t2 t0. At time t2, Qn−1 has a binary “0” value when the clock CLK rises. Thus, since Qn previously had a binary “1” value, and Qn−1 had a binary “0” value when the clock CLK rose, the value of Qn changes to binary “0” shortly after time t2. Unlike FIG. 4A, which had no clock skew, with clock skew, the value of clock CLK changes at time t2, which is after the time when the value of Qn−1 changed at t1. When the next active edge of the clock CLK occurs at time t5, Qn−1 has a binary “1” value. Thus, the value of Qn changes to binary “1” shortly after time t5.
Therefore, during test mode operation of the mux scan chain 30, the hold time condition of the Qn−1 signal is not satisfied with respect to the active edge of the clock CLK when there is clock skew. This is because the value of Qn−1 changes just before the active edge of the clock CLK. Specifically, Qn−1 changes at time t1 (as shown in FIG. 4B), which is before the active edge of the clock CLK at time t2. This hold time violation is caused by the fact that during test mode, signal Qn−1 does not travel through the combinational logic 32, which makes the signal Qn−1 reach the flip-flop 14 of the first mux scan cell 11 sooner than it would in normal mode. In addition, the path delay taken during test mode is smaller than in normal mode, and this path delay is less than the amount of time that the clock is skewed by.
Thus, timing conditions from running the mux scan chain 30 in normal mode and test mode are not the same. Clearly, the test mode is not capable of providing proper timing tests on the mux scan chain 30 since hold time violations are occurring. This reduces the worth of the test mode, and can possibly lead to incorrect design of the mux scan chain 30 if proper care is not taken to consider propagation delay caused by the combinational logic 32.